Design and FPGA Implementation of Configurable Interference Waveforms for Embedded SDR Systems

Abstract

With the continuous evolution of wireless communication systems in terms of architectures, operating frequency bands, and network structures, the communication environment has become increasingly complex and exhibits diversified characteristics. In communication system testing, electromagnetic environment simulation, and countermeasure scenario research, higher requirements have been put forward for the flexibility of jamming signals regarding waveform types, parameter configuration, and transmission modes. However, traditional communication jamming equipment generally suffers from large volume, fixed functionality, and limited waveform types, making it difficult to adapt to rapidly changing application requirements. To address the above issues, this paper designs and implements a configurable jamming waveform generation platform based on an SDR system, focusing on the digital generation methods of various typical jamming waveforms on embedded FPGA platforms. The system utilizes the Zynq-7020 SoC as the signal processing core, combined with the AD9361 integrated RF transceiver chip, to construct a highly integrated baseband processing and RF transmission platform. Parameterized generation and modulation of various jamming waveforms—including single-tone, multi-tone, sweeping-frequency, and broadband noise—are implemented in the Programmable Logic side, with waveform parameter configuration and system operation control completed through the Processing System. Experimental results demonstrate that under limited volume and power consumption conditions, the system can stably generate multiple jamming signal forms, and its RF output spectral characteristics remain consistent with theoretical analysis results, verifying the feasibility and effectiveness of the proposed jamming waveform FPGA implementation method and system architecture.