Design and Implementation of 1553B Bus Simulator - MT

Abstract

This paper focuses on the modeling and simulation of the MT mode of the 1553B bus protocol processor B64843GC. Built on the QEMU platform, a dual-track mechanism is implemented that can be freely switched between word monitor and selective message monitor modes. It not only captures every command, data, and status word on the bus without omission, but also records only critical messages by programming multidimensional filters such as RT address, sub-address, and T/R bit, significantly reducing storage and post-analysis overhead. The system fully supports RT/MT combined mode, allowing the processor to respond to local messages as a remote terminal while still keeping full monitor coverage of communication among other terminals. Complemented by interrupt management, cyclic stack, auto-wrap, and error detection mechanisms, it performs real-time tagging of anomalies like format errors, no-response, word-count mismatch, and message supersession, forming a closed monitor loop that covers the full life cycle of "start-transfer-end". Simulation results verify the stability and real-time performance of the solution under high-load, multi-node, and complex topologies, providing an efficient, flexible, and low-cost virtual verification means for debugging, fault analysis, and data logging of 1553B systems, and can be directly applied to development and test flows in safety-critical fields such as avionics, shipboard, and vehicle platforms.